1. Fields of the Invention
The present invention relates to a method and an apparatus for forming an ohmic contact to a metallization layer in an insulating film on an amorphous Si, which is an active layer, particularly in a method for manufacturing thin film devices on a glass substrate.
2. Description of the Related Art
Thin film semiconductor devices have been widely used as pixel drivers for displays in wide-screen displays, personal computers, mobile phones and the like. Among amorphous silicon, polycrystalline silicon (hereafter abbreviated as poly-Si) is promising as the material for the semiconductor layers of the thin film semiconductor devices. This is because poly-Si has high mobility, and favorable switching characteristics can be obtained. The method for manufacturing a thin film semiconductor device using poly-Si is similar to the conventional method for manufacturing an Si semiconductor device.
However, the process for forming a thin film semiconductor device is different from the process for forming a conventional Si semiconductor device, in that the Si semiconductor device uses an Si substrate, while the thin film semiconductor device uses a glass substrate, and uses laser annealing for poly-crystallizing an Si thin film. Therefore, the thin film semiconductor process has inherent problems that do not arise in the conventional Si semiconductor process.
One of the exemplary problems is that it is difficult to get sufficiently low contact resistance at contact hole. The contact hole is normally formed by opening a contact hole in an insulating film coating a thin film semiconductor, which becomes an active layer, using etching; burying an upper wiring therein; and connecting the upper wiring to the thin film semiconductor.
As described above, since poly-Si is undergone laser annealing, the surface thereof is not planarized, and has an irregular structure depending on the intensity distribution of the laser. Therefore, the insulating film formed in the concave portions of the poly-Si surface cannot be completely removed by etching, and often remains in the concave portions, causing the elevation of contact resistance. In such an irregular structure, byproducts of etching are also easily accumulated, causing the further elevation of contact resistance. In order to solve the problem, contact holes were conventionally formed by the combined use of dry etching and wet etching. This will be specifically described referring to FIGS. 5 (a)-5 (d).
First, as FIG. 5 (a) shows, an Si oxide film 102 of a thickness of about 300 nm is formed on a glass substrate 101, and an active layer Si film 103 of a thickness of 60 nm is formed thereon. Then, excimer laser beams are irradiated on the surface of the active layer Si film 103, and is crystallized to form a poly-Si film.
Next, an Si oxide film 104 of a thickness of 50 nm is formed, and a micro-crystalline silicon (μc-Si) film 105 and a Cr film 106 are formed in this order as a gate wiring. Here, the thickness of the μc-Si film 105 is 100 nm, and the thickness of the Cr film 106 is 200 nm.
Next, the μc-Si film 105 and the Cr film 106 are patterned by photolithography to form a gate electrode. Next, an Si oxide film of a thickness of 100 nm is formed thereon, and heat treatment at a temperature of 350° C. or above is performed to lower the resistance of the poly-Si film. Then, an Si oxide film of a thickness of 300 nm is further formed to form an interlayer film 107 of a total thickness of 400 nm.
Therefore, the thickness of the interlayer insulating film on the gate electrode becomes 400 nm, and the film thickness on the active layer Si film 103 becomes the sum of the thicknesses of the Si oxide film 104 and the Si oxide film 107, i.e., 450 nm.
Next, as FIG. 5 (b) shows, contact opening is performed in the interlayer film 107 to the Cr film 106 and to the active layer Si film 103. The SiO2 film is etched by reactive etching using a photoresist film 108 as a mask to open contact holes extending to the Cr film 106 and to the active layer Si film 103, respectively. Here, since the thickness of the Si oxide film on the active layer Si film 103 is 450 nm, while the thickness of the Si oxide film on the Cr film 106 is 400 nm, the contact hole on the gate Cr is first opened by the etching. Although the contact hole on the Cr film 106 is over-etched when the contact hole on the active layer Si film 103 is formed, the Cr film 106 is not etched at all if the CHF3+O2 gas 109 is used as the etching gas. Therefore, excessive removal by over-etching does not occur.
The method for removing the Si oxide film using CHF3+O2 as the etching gas is described in Japanese Patent Application Publication No. 2001-274411A. The fluorocarbon-based byproducts of the etching 110 deposited on the active layer Si film 103 during etching are removed by wet etching 111 using buffered hydrofluoric acid as FIG. 5 (c) shows.
The method to use hydrofluoric acid-based etchant for thus removing the fluorocarbon-based byproducts of the etching on the active layer Si film is described in Japanese Patent Application Publication No. 11-111988A.
Finally, as FIG. 5 (d) shows, after peeling off the photoresist film, transferring the glass substrate 101 into the sputtering apparatus, performing AlSi sputtering 112, and forming an AlSi film as a drain wiring, a gate Cr/Al contact 113 and an Si active layer/Al contact 114 are buried, and the Cr film 106 is connected to the active layer Si film 103 by the AlSi film.
Here, the time from the wet etching step using BHF shown in FIG. 5 (c) to the AlSi sputtering step shown in FIG. 5 (d) must be one day or less so as to prevent the formation of a surface-oxidized silicon film. This is because the time when the Si surface is H-terminated by the etching, and the formation of a surface-oxidized silicon film is suppressed at longest for about 24 hours.
In a conventional process for forming contact holes, as described above, two types of etching, ion etching and wet etching, are performed on the insulating film on an active layer Si film. However, the irregularity on the surface of the active layer Si film cannot be completely planarized.
Particularly, it is extremely difficult to remove the Si oxide film remaining under the byproducts of the etching. Therefore, the contact resistance cannot be controlled at high reproducibility. In particular, this effect is significant in the case of fine contact patterns, resulting in a defective contact. To avoid this problem, a method to set the endpoint of dry etching on the active layer Si film has been used. This will be described referring to FIGS. 6 (a)-6 (d) showing an enlarged contact hole area on the active layer Si film. As FIG. 6 (a) shows, the surface of the active layer Si film 103 has an irregular structure with a height difference of about 20 nm after the radiation of the excimer laser. To control Si oxide films remaining in the concave portion, the endpoint of dry etching shown in FIG. 6 (b) is the depth wherein the active layer Si film 103 is partly over-etched. By etching to this depth, the irregularity of the surface of the active layer Si film 103 is reduced, and the Si oxide films 115 remaining in the concave portion shown in FIG. 6 (b) can be easily removed by BHF wet etching together with the byproducts of the etching 110 as shown in FIG. 6 (c). Finally, as FIG. 6 (d) shows, the gate Cr/Al contact 113 is connected to the Si active layer/Al contact 114 by forming the AlSi sputtered film after removing the photoresist film 108. Here, the thickness of the active layer Si film 103 is 60 nm, and although an impurity phosphorus  (hereafter, abbreviated as P) is distributed down to the depth of about 20 nm, the P concentration lowers sharply in the deeper portion (FIG. 7).
Therefore, the region where the removal by over-etching is allowed is limited to the depth of about 20 nm from the surface. The accuracy of controlling the etching depth in dry etching is at most 100 nm, and such accurate controlling is considerably difficult. When the daily fluctuation of the etching rate and change of the apparatus itself over time are considered, the optimization of etching time for every etching is required. Thus, the lowering of throughput and increase in manufacturing costs due to such process optimization is inevitable.